A clock signal may reach different parts of a memory circuit through different paths and hence at different times. Process variations and variations in associated voltage supply can add to these time differences. Such time differences can cause incorrect read or write operations. Tracking circuits have been used to compensate for these time differences. However, the tracking circuits operate on a worst-case basis and hence the tracking circuits degrade performance of the memory circuit. In a retention-till-access (RTA) memory, an RTA mode of operation accounts for worst-case timing differences. The tracking circuit operates on the worst-case basis even when the memory circuit is not being operated in the RTA mode. Hence, there is a need for a way to compensate for the timing differences in the memory circuit, in one or more modes of operation, with minimal performance degradation.